rabin K.
Senior Physical Design Engineer
Open to offersNew to PlatformAbout
Rabin K. is a seasoned Physical Design Engineer based in Bangalore with 7 years of hands-on experience in the semiconductor and electronics industries. He has contributed to advanced technology nodes—ranging from 2nm, 3nm, 4nm, 7nm, 10nm, 14nm, to 32nm—at organizations including Aritrak Technologies, Microsoft, LeadSOC Technologies, Insemi Technologies, Synapse Techno Design, Si2Chip Technologies, Bangalore Semiconductor Services, and Mindlance Technologies. Rabin has executed complex floor planning, power planning, placement, clock tree synthesis, and routing tasks for high-profile projects like graphics processors at MEDIATEK, server MPU blocks at AMD, and memory projects at Samsung Institute of Research and Intel. His technical acumen spans timing analysis, leakage recovery, design rule fixes, and ECOs, leveraging leading EDA tools such as Fusion Compiler, ICC2, Innovus, and PrimeTime. Rabin is also adept in script writing with TCL and PERL, and has consistently addressed timing closure challenges up to 2.2GHz frequency environments.
Experience
Physical Design Engineer
Aritrak Technologies · 2025 — 2026Executed physical-aware synthesis for six critical blocks, focusing on optimizing both performance and area. Conducted thorough timing QoR analysis and applied effective fixes for timing violations. Carried out formal verification following synthesis and performed low power verification. Validated timing constraints to maintain design integrity.Physical Design Engineer
LeadSOC Technologies · 2025 — 2025Implemented physical design for the ORCA_TOP block utilizing 32nm technology. Conducted experiments with various floorplans and analyzed multiple frequencies.Physical Design Engineer
Insemi Technologies · 2024 — 2025Implemented the physical design for the ORCA_TOP block using 32nm technology. Optimized floorplan architecture through iterative adjustments to enhance power and area targets. Analyzed design performance across different operating frequencies.Lead Engineer
Synapse Techno Design Pvt. Ltd. · 2020 — 2023Coordinated efforts across four blocks while addressing floorplan issues related to the Graphics Processor developed with 4nm technology.Senior Physical Design Engineer
Synapse Techno Design Pvt. Ltd. · 2020 — 2022Implemented physical design across several blocks for a Server MPU project. Resolved issues related to placement, clock tree synthesis, and routing. Performed PNR, ECO, timing closure, DRV, and DRC fixes, as well as RDL routing including base and metal ECO.Physical Design Engineer
Si2Chip Technologies Pvt. Ltd. · 2018 — 2020Executed physical design for a block in 7nm technology using Innovus, achieving timing closure with PrimeTime at a frequency of 1.5GHz. Managed the floorplan and placement involving 1835 ports and 1.4M instances. Completed clock tree synthesis and routing activities, alongside static timing analysis across four modes and 40 PVT corners.Physical Design Engineer
Bangalore Semiconductor Services · 2017 — 2018Engaged in the Intel IVY CREEK Testchip project within 10nm technology encompassing six hard macros at a frequency of 334MHz. Addressed responsibilities including floorplanning, placement, clock tree synthesis, routing, and static timing analysis while overcoming timing violations related to power discontinuity and unclocked registers using ICC2 and PrimeTime.Physical Design Engineer
Bangalore Semiconductor Services · 2017 — 2018Focused on ECO timing fixes, leakage recovery, and DRV for the Lakefield project, utilizing PrimeTime and ICC2 within the 10nm technology framework.Physical Design Engineer
Mindlance Technologies · 2017 — 2017Participated in the Intel 14nm Test chip project with a focus on the XE_XBAR_WRAPPER block, which included 32 macros and 250,000 instances. Handled placement, clock tree synthesis, and routing while managing challenges such as timing violations and bound placement using ICC and PrimeTime.Physical Design Engineer
Si2ChipWorked on the DMA_MAC dummy block with low power implementation in 45nm technology using Innovus. Conducted block-level design comprising seven hard macros, achieving a frequency of 500MHz. Managed the floorplan, power plan, placement, clock tree synthesis, and routing while addressing challenges related to power domains and clock tree building.
Skills & Expertise
Education
- B.E. in Electrical and ElectronicsSathyabama university, Chennai